AZIZ, S. M.; AHMED, I. Easily Testable Array Multiplier Design Using VHDL. Malaysian Journal of Computer Science, [S. l.], v. 11, n. 2, p. 1–7, 1998. Disponível em: https://jpmm.um.edu.my/index.php/MJCS/article/view/5722. Acesso em: 25 nov. 2024.